The present invention generally relates to a connection, system and method of phase delayed synchronization in high speed digital systems using delay elements, and more particularly relates to a phase delay arrangement wherein a substantial majority of delay is provided via added passive delay elements.
In FIG. 1, there is illustrated a high speed digital system 100 including a driving circuit 110 receiving a signal SIG and outputting a processed such signal to a receiving circuit 130 via an existing connection circuit 120 and connectors C, such driving circuit 110 and receiving circuit 130 being driven by a common clock signal CLK provided along a clock line 140. The driving circuit 110 and receiving circuit 130 can be any type of driving and receiving circuit. The components within the driving circuit 110 and receiving circuit 130 (e.g., both which may be implemented via IC chips) are manufactured to have sub-micron dimensions and micron spacings between such components, and accordingly, signal propagation time from one internal IC element to another internal IC element is substantially negligible. As a result, the internal IC circuits operate at extremely high speeds, e.g., server chips sets typically now operate with internal clock speeds of 100 MHz or faster. The present invention arises from the problem that external component spacings outside of the ICs (e.g., spacing between IC chips) are not matching the component spacings within ICs making it difficult if not impossible to manage synchronization with respect to downstream signals.
More particularly, in contrast to the internal environment of the ICs, in the FIG. 1 environment external to the ICs, there are physical limitations as to how closely spaced a driving circuit 110 and a receiving circuit 130 can be placed. More specifically, in this age of complex, highly dense systems having a plurality of interconnected printed circuit boards (PCBs) having several tens/hundreds of IC chips, a tremendous number of interconnection lines, numerous connectors and several hundreds/thousands of supporting components (e.g., resistors, capacitors, inductors, etc.), often a driving circuit 110 and a receiving circuit 130 are physically limited to be spaced at a substantial distance D (e.g., ten to fifteen inches) from one another. Resultant signal propagation along the substantial distance D, and especially through connectors C and any existing circuit 120 may cause a propagating signal not to meet a setup time of the receiving circuit 130, i.e., cause a synchronization mismatch between the driving/receiving circuits.
More specifically, assuming that the signal SIG is processed and output by the driving circuit 110 at a time t=0 (FIG. 2) coincident with a first clock pulse 242 of a 100 MHz (i.e., megahertz) clock having 10 ns (i.e., nanoseconds) clock periods, and does not arrive at the receiving circuit input until 13 ns later, such signal cannot be input into the receiving circuit 130 upon occurrence of the second clock pulse 244, i.e., it arrives too late at the receiving circuit. As a further problem, it is unlikely that such output signal will remain prevalent (i.e., valid) at an input to the receiving circuit 130 for another 6-7 nS so as to be available for capturing by the receiving circuit 130 upon occurrence of a third clock pulse 246. Accordingly, a window of availability of the propagated output signal at the receiving circuit 130""s input does not match a predetermined setup time window required by the receiving circuit 130. A first method to deal with such signal propagation mismatch is to repeatedly rearrange IC""s within a complex system (i.e., redesign) in an attempt to minimize IC-to-IC distances, but such method is limited because eventually physical spacing limitations are reached.
A second method of dealing with signal propagation mismatch is to utilize a multi-stage synchronous system such as that shown in FIG. 3 in order to synchronously control intermittent propagation timing of the output signal from the driving circuit 110 to the receiving circuit 130. More particularly, the FIG. 3 system 300 includes a multi-stage synchronous system 350 including a plurality of edge-triggered flip flops 360, 360+n (where n is an integer, e.g., 3-5), which flip flops 360, 360+n are clocked utilizing the common clock signal CLK along the clock signal line 140xe2x80x2. More specifically, the edge-triggered flip flops are utilized to control intermittent propagation of the output signal in its travel from the driving circuit 110 to the receiving circuit 130 so as to adjust a signal availability window at an input to the receiving circuit 130 to match an input timing requirement of the receiving circuit 130, i.e., to arrive at the input of the receiving circuit 130 at 19 nS which is immediately before the third clock pulse 246 occurring at 20 nS from the time t=0 as shown in FIG. 2. Accordingly, although the original propagated output signal cannot be available for the second clock pulse 244, such propagated output signal can be adjusted in time to be available for the third clock pulse 246.
The problems with the FIG. 3 multi-stage synchronous arrangement are numerous. More specifically, first, additional components are required to be added to the system 300, thus drastically increasing a crowding density and complexity of the system. For example, if there are 32 data bit output lines between a driving circuit 110 and a receiving circuit 130, and if two edge-triggered flip flops are required for each data line, then, 64 additional flip flops, clock lines and flip-flop power connections (Vcc and ground connections; not shown) would have to be provided between a single driving-circuit/receiving-circuit pair. If a compound number of driving/receiving circuit pairs exist within a system, a number of required additional components is compounded even more. Such numbers drastically increase a complexity of designing such a system 400, and often, multi-layered printed circuit boards (PCBc) are required to accommodate the tremendous number of conduction lines required. Further, since the flip-flops are active components, a power consumption and heat generation of the system is increased.
Both the redesigning approach and multi-stage synchronous arrangement represent a substantial time and money investment, and both degrade a time to market (TTM) introduction and availability new systems. As semiconductor manufacturing technology progresses to allow smaller and more closely spaced semiconductor elements within an integrated circuit (IC), the internal operating clock speeds of such ICs will continue to increase dramatically. As internal IC operating speeds become faster and faster, propagation problems caused by external spacing limitations will become more and more of a problem.
The present invention is related to theory and method of phase delayed synchronization in high speed digital systems. More particularly, the present invention relates to a circuit connection including: a phase delay synchronizer adapted to connect two digital circuits and provide phase delay synchronization between the digital circuits in order to make a propagating output signal from a transmitting one of the digital circuits meet a predetermined valid data input timing requirement of a receiving one of the digital circuits, wherein delay is provided substantially by at least one passive delay element.